The IEEE 1149.1 standard defines an IC level boundary test architecture and serial interface that simplifies testing of ICs and boards. An IC incorporating the 1149.1 boundary scan test architecture is shown in FIG. 1. The test architecture consists of a test access port (TAP), serial output circuit, instruction register, and three data registers, comprising; a scan bypass register, a boundary scan register, and an identification register.
The TAP responds to test clock (TCK) and test mode select (TMS) inputs to shift data through either the instruction register or a selected data register from the test data input (TDI) to the test data output (TDO). The output circuit allows multiplexing the serial output of the instruction or a selected data register to TDO. The instruction register provides storage for test commands input into the architecture. The boundary scan register is associated with the IC's inputs and outputs and provides the test circuitry required for testing the wiring interconnects between ICs on a board as well as for testing the application logic of the host IC. The bypass register provides an abbreviated single bit scan path through the IC when boundary testing is not being performed. The identification register provides information about the IC.
The TAP is a finite state machine comprising 16 states. The TAP has inputs for externally receiving a clock input via the TCK pin, a control input via the TMS pin, and a reset input via the optional test logic reset (TRST) pin. The TAP has outputs for internally supplying control to reset the test architecture, execute test instructions, and scan data through the test architecture from TDI to TDO. The TAP responds to serial protocol input via the TMS pin to transition through its predefined states during scan and test operations.
In the state diagram of FIG. 2, it is seen that the TAP consists of 6 steady states: test logic reset (TLRST), run test/idle (RT/IDLE), shift data register (SHIFT-DR), pause data register (PAUSE-DR), shift instruction register (SHIFT-IR), and pause instruction register (PAUSE-IR). The names of these steady states indicate their function, i.e. TLRST resets the test logic, RT/IDLE runs self tests or idles the test logic, SHIFT-DR/IR shifts data from TDI to TDO, and PAUSE-DR/IR pauses the shifting of data from TDI to TDO.
Transitions between steady states as well as required test actions are achieved via 10 temporary states: select data register scan (SELDRS), capture data register (CAPTURE-DR), exit1 data register (EXIT1-DR), exit2 data register (EXIT2-DR), update data register (UPDATE-DR), select instruction register scan (SELIRS), capture instruction register (CAPTURE-IR), exit1 instruction register (EXITI-IR), exit2 instruction register (EXIT2-IR), and update instruction register (UPDATE-IR).
During instruction and data register scan operations, the TDO output is enabled to output data while the TAP is in the SHIFT-DR or SHIFT-IR states. Also, during the SHIFT-DR and SHIFT-IR states, data is clocked into the test architecture from TDI on the rising edge of TCK and output from the test architecture on TDO on the falling edge of TCK.
The TAP polices the activity of the test architecture using seven well defined operation modes; (1) a reset mode, (2) an idle mode, (3) a data scan mode, (4) a pause data scan mode, (5) an instruction scan mode, (6) a pause instruction scan mode, and (7) a run test mode. The benefit of having well defined operation modes is that it insures test and scan access compatibility among ICs from different vendors.
The reset mode is achieved by forcing the TAP into the TLRST state either by control input from TMS or by activation of the TRST input. In the reset mode, the TAP outputs a reset signal to the test architecture forcing it to remain in an inactive state. The TAP should be in the TLRST state whenever the IC is in its mission mode to prevent the test logic from disturbing system operation.
The idle mode is achieved by loading the instruction register with a benign instruction, then transitioning the TAP into the RT/IDLE state. In the idle mode, the test architecture is not reset, as in the reset mode, but rather it is in a condition where test and scan operations are temporarily suspended.
The data scan mode is achieved by sequencing the TAP through a series of states entered via the SELDRS state of FIG. 2. During the data scan mode, a selected data register receives control from the TAP to perform a predefined set of test steps, comprising; (1) a capture step (CAPTURE-DR), (2) shift step (SHIFT-DR), and (3) an update step (UPDATE-DR). The capture step causes the selected data register to parallel load with data. The shift step causes the selected data register to shift data from TDI to TDO. The update step causes the selected data register to parallel output the data it received during the shift step. Data register selection is determined by the instruction in the instruction register.
The pause data scan mode is used to suspend the transfer of data through the selected data register from TDI to TDO during the data scan mode's shifting step. The pausing of data scans is accomplished by causing the TAP to enter into the PAUSE-DR state of FIG. 2.
The instruction scan mode is achieved by sequencing the TAP through a series of states entered via the SELIRS state of FIG. 2. During the instruction scan mode, the instruction register receives control from the TAP to perform a predefined set of test steps, comprising; (1) a capture step (CAPTURE-IR), (2) shift step (SHIFT-IR), and (3) an update step (UPDATE-IR). The capture step causes the instruction register to parallel load with status information. The shift step causes the instruction register to shift data from TDI to TD0. The update step causes the instruction register to parallel output the instruction data it received during the shift step.
The pause instruction scan mode is used to suspend the transfer of data through the instruction register from TDI to TDO during the instruction scan mode's shifting step. The pausing of instruction scans is accomplished by causing the TAP to enter into the PAUSE-IR state of FIG. 2.
The run test mode is achieved by loading a self-test instruction into the instruction register, then transitioning the TAP into the RT/IDLE state. When the TAP enters the RT/IDLE state the self-test starts and continues while the TAP is in the RT/IDLE state. The self-test is stopped either automatically by the design of the self-testing circuitry or by transitioning the TAP out of the RT/IDLE state. The minimum number of TCK cycles the TAP is required to remain in the RT/IDLE state is determined by the self-test operation being performed.
To provide for scan access flexibility, the TAP allows ICs on a board or boards in a backplane to be connected in either a 1149.1 ring or star bus configuration.
In a backplane 1149.1 ring configuration of FIG. 3, all boards directly receive the TCK and TMS control outputs from the TBC and are daisy chained between the TBC's TDO output and TDI input. During scan operation, the TBC outputs control on TMS and TCK to scan data through all boards in the backplane, via its TDO and TDI bus connections. In the ring configuration all boards are enabled simultaneously to be serially accessed and tested by the TBC.
A problem associated with the ring configuration, is that the scan operation only works if all the boards are included in the backplane and are operable to scan data from their TDI input to TDO output. If one of the boards is removed or has a fault, the TBC will be unable to scan data through the backplane. Since the ring configuration does not allow access to remaining boards when one is removed or disabled, it does not fully meet the needs of a backplane serial bus.
In a backplane 1149.1 star configuration of FIG. 4, all boards directly receive the TCK and TDI signals from the TBC and output a TDO signal to the TBC. Also each board receives a unique TMS signal from the TBC. In the star configuration only one board is enabled at a time to be serially accessed and tested by the TBC. When a board is enabled, the TMS signal associated with that board will be active while all other TMS signals are inactive.
A problem with the star configuration is that each board requires its own TMS signal. In a backplane with 50 boards, the TBC would have to have 50 individually controllable TMS signals, and the backplane would have to have traces for each of the 50 TMS signals. Due to these requirements, star configurations are typically not considered for backplane applications.
The present invention allows a TBC to selectively enable a plurality of applications associated with a given test bus, and cause the applications to simultaneously execute test operations in a unified fashion.